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general description the max5062/max5063/max5064 high-frequency, 125v half-bridge, n-channel mosfet drivers drive high- and low-side mosfets in high-voltage applications. these drivers are independently controlled and their 35ns typical propagation delay, from input to output, are matched to within 3ns (typ). the high-voltage operation with very low and matched propagation delay between drivers, and high source/sink current capabilities in a thermally enhanced package make these devices suit- able for the high-power, high-frequency telecom power converters. the 125v maximum input voltage range pro- vides plenty of margin over the 100v input transient requirement of telecom standards. a reliable on-chip bootstrap diode connected between v dd and bst elimi- nates the need for an external discrete diode. the max5062a/c and the max5063a/c offer both nonin- verting drivers (see the selector guide ). the max5062b/d and the max5063b/d offer a noninverting high-side driver and an inverting low-side driver. the max5064a/b offer two inputs per driver that can be either inverting or noninverting. the max5062a/b/c/d and the max5064a feature cmos (v dd / 2) logic inputs. the max5063a/b/c/d and the max5064b feature ttl logic inputs. the max5064a/b include a break-before- make adjustment input that sets the dead time between drivers from 16ns to 95ns. the drivers are available in the industry-standard 8-pin so footprint and pin configura- tion, and a thermally enhanced 8-pin so and 12-pin (4mm x 4mm) thin qfn packages. all devices operate over the -40? to +125? automotive temperature range. applications telecom half-bridge power supplies two-switch forward converters full-bridge converters active-clamp forward converters power-supply modules motor control features ? hip2100/hip2101 pin compatible (max5062a/ max5063a) ? up to 125v input operation ? 8v to 13.2v v dd input voltage range ? 2a peak source and sink current drive capability ? 35ns typical propagation delay ? guaranteed 8ns propagation delay matching between drivers ? programmable break-before-make timing (max5064) ? up to 1mhz combined switching frequency while driving 100nc gate charge (max5064) ? available in cmos (v dd / 2) or ttl logic-level inputs with hysteresis ? up to 15v logic inputs independent of input voltage ? low 2.5pf input capacitance ? instant turn-off of drivers during fault or pwm start-stop synchronization (max5064) ? low 200a supply current ? versions available with combination of noninverting and inverting drivers (max5062b/d and max5063b/d) ? available in 8-pin so, thermally enhanced so, and 12-pin thin qfn packages max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers ________________________________________________________________ maxim integrated products 1 part temp range pin- package top mark max5062 aasa* -40? to +125? 8 so max5062basa* -40? to +125? 8 so max5062casa* -40? to +125? 8 so-ep** max5062dasa* -40? to +125? 8 so-ep** ordering information part high-side driver low-side driver logic levels pin compatible max5062aasa noninverting noninverting cmos (v dd / 2) hip 2100ib max5062basa noninverting inverting cmos (v dd / 2) max5062casa noninverting noninverting cmos (v dd / 2) max5062dasa noninverting inverting cmos (v dd / 2) selector guide 19-3502; rev 0; 11/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. selector guide continued at end of data sheet . * future product? ontact factory for availability. ** ep = exposed paddle. ordering information continued at end of data sheet.
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = v bst = +8v to +13.2v, v hs = gnd = 0v, bbm = open, t a = -40? to +125?, unless otherwise noted. typical values are at v dd = v bst = +12v and t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd, unless otherwise noted.) v dd , in_h, in_l, in_l+, in_l-, in_h+, in_h-........-0.3v to +15v dl, bbm .....................................................-0.3v to (v dd + 0.3v) hs............................................................................-5v to +130v dh to hs.....................................................-0.3v to (v dd + 0.3v) bst to hs ...............................................................-0.3v to +15v dv/dt at hs ........................................................................50v/ns continuous power dissipation (t a = +70?) 8-pin so (derate 5.9mw/? above +70?)...............470.6mw 8-pin so with exposed pad (derate 19.2mw/? above +70?)......................................................1538.5mw 12-pin thin qfn (derate 24.4mw/? above +70?)......................................................1951.2mw maximum junction temperature .....................................+150? operating temperature range .........................-40? to +125? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units power supplies operating supply voltage v dd 8.0 13.2 v max5062_/ max5063_ 70 140 v dd quiescent supply current i dd in_h = in_l = gnd (no switching) max5064_ 120 260 ? v dd operating supply current i ddo f sw = 500khz, v dd = +12v 3 ma bst quiescent supply current i bst in_h = in_l = gnd (no switching) 15 40 ? bst operating supply current i bsto f sw = 500khz, v dd = v bst = +12v 3 ma uvlo (v dd to gnd) uvlo vdd v dd rising 6.5 7.3 8.0 v uvlo (bst to hs) uvlo bst bst rising 6.0 6.9 7.8 v uvlo hysteresis 0.5 v logic input max5062_/max5064a, cmos (v dd / 2) version 0.67 x v dd 0.55 x v dd input-logic high v ih_ max5063_/max5064b, ttl version 2 1.65 v max5062_/max5064a, cmos (v dd / 2) version 0.4 x v dd 0.33 x v dd input-logic low v il_ max5063_/max5064b, ttl version 1.4 0.8 v max5062_/max5064a, cmos (v dd / 2) version 1.6 logic-input hysteresis v hys max5063_/max5064b, ttl version 0.25 v
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = v bst = +8v to +13.2v, v hs = gnd = 0v, bbm = open, t a = -40? to +125?, unless otherwise noted. typical values are at v dd = v bst = +12v and t a = +25?.) (note 1) parameter symbol conditions min typ max units v in_h+ , v in_l+ = 0v v in_l = v dd for max5062b/d, max5063b/d v in_h- , v in_l- , v in_h = v dd logic-input current i_in v in_l = 0v for max5062a/c, max5063a/c -1 0.001 +1 ? in_h+, in_l+ in_h, to gnd in_l to v dd for max5062b/d, max5063b/d in_h-, in_l-, in_h, to v dd input resistance r in in _l fo r max5062a/c, max5063a/c to gnd 1m ? input capacitance c in 2.5 pf high-side gate driver hs maximum voltage v hs_max 125 v bst maximum voltage v bst_max 140 v t a = +25? 2.5 3.3 driver output resistance (sourcing) r on_hp v dd = 12v, i dh = 100ma (sourcing) t a = +125? 3.5 4.6 ? t a = +25? 2.1 2.8 driver output resistance (sinking) r on_hn v dd = 12v, i dh = 100ma (sinking) t a = +125? 3.2 4.2 ? dh reverse current (latchup protection) (note 2) 400 ma power-off pulldown clamp voltage v bst = 0v or floating, i dh = 1ma (sinking) 0.94 1.16 v peak output current (sourcing) c l = 10nf, v dh = 0v 2 a peak output current (sinking) i dh_peak c l = 10nf, v dh = 12v 2 a low-side gate driver t a = +25? 2.5 3.3 driver output resistance (sourcing) r on_lp v dd = 12v, i dl = 100ma (sourcing) t a = +125? 3.5 4.6 ? t a = +25? 2.1 2.8 driver output resistance (sinking) r on_ln v dd = 12v, i dl = 100ma (sinking) t a = +125? 3.2 4.2 ? reverse current at dl (latchup protection) (note 2) 400 ma power-off pulldown clamp voltage v dd = 0v or floating, i dl = 1ma (sinking) 0.95 1.16 v peak output current (sourcing) i pk_lp c l = 10nf, v dl = 0v 2 a peak output current (sinking) i pk_ln c l = 10nf, v dl = 12v 2 a internal bootstrap diode forward voltage drop v f i bst = 100ma 0.91 1.11 v turn-on and turn-off time t r i bst = 100ma 40 ns
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers 4 _______________________________________________________________________________________ note 1: all devices are 100% tested at t a = +125?. limits over temperature are guaranteed by design. note 2: guaranteed by design, not production tested. note 3: break-before-make time is calculated by t bbm = 8ns x (1 + r bbm / 10k ? ). electrical characteristics (continued) (v dd = v bst = +8v to +13.2v, v hs = gnd = 0v, bbm = open, t a = -40? to +125?, unless otherwise noted. typical values are at v dd = v bst = +12v and t a = +25?.) (note 1) parameter symbol conditions min typ max units switching characteristics for high- and low-side drivers c l = 1000pf 7 c l = 5000pf 33 rise time t r c l = 10,000pf 65 ns c l = 1000pf 7 c l = 5000pf 33 fall time t f c l = 10,000pf 65 ns cmos 30 55 turn-on propagation delay time t d_on figure 1, c l = 1000pf (note 2) ttl 35 63 ns cmos 30 55 turn-off propagation delay time t d_off figure 1, c l = 1000pf (note 2) ttl 35 63 ns delay matching between inverting input to output and noninverting input to output t match1 c l = 1000pf, bbm open for max5064, figure 1 (note 2) 28ns delay matching between driver- low and driver-high t match2 c l = 1000pf, bbm open for max5064, figure 1 (note 2) 28ns r bbm = 10k ? 16 r bbm = 47k ? (notes 2, 3) 40 56 72 break-before-make accuracy (max5064 only) r bbm = 100k ? 95 ns internal nonoverlap 1ns
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers _______________________________________________________________________________________ 5 undervoltage lockout (v dd and v bst rising) vs. temperature max5062/3/4 toc01 temperature ( c) uvlo (v) 110 95 65 80 -10 5 20 35 50 -25 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 7.5 6.5 -40 125 uvlo vdd uvlo bst v dd and bst undervoltage lockout hysteresis vs. temperature max5062/3/4 toc02 temperature ( c) uvlo hysteresis (v) 110 95 65 80 -10 5 20 35 50 -25 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -40 125 uvlo bst hysteresis uvlo vdd hysteresis i dd vs. v dd max5062/3/4 toc03 40 s/div v dd 2v/div 500 a/div 0a 0v i dd max5064 in_l-, in_h- = v dd in_l+, in_h+ = gnd i ddo + i bsto vs. v dd (f sw = 250khz) max5062/3/4 toc04 v dd (v) i ddo + i bsto (ma) 12 10 11 3456789 12 1.0 0.8 0.6 0.4 0.2 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 0 013 0 60 40 20 80 100 120 140 160 180 200 0.5 0.7 0.6 0.8 0.9 1.0 1.1 internal bst diode (i-v) characteristics max5062/3/4 toc05 v dd - v bst (v) i diode (ma) t a = +125 c t a = +25 c t a = 0 c t a = -40 c 0 60 40 20 80 100 120 140 160 04 26810 15 37911121 31415 v dd quiescent current vs. v dd (no switching) max5062/3/4 toc06 v dd (v) i dd ( a) t a = -40 c t a = +125 c max5064 t a = +25 c, t a = 0 c 0 6 3 9 12 15 18 21 04 26810 15 37911121 31415 bst quiescent current vs. bst voltage max5062/3/4 toc07 v bst (v) i bst ( a) v bst = v dd + 1v, no switching t a = +125 c t a = -40 c, t a = 0 c, t a = +25 c t ypical operating characteristics (typical values are at v dd = v bst = +12v and t a = +25?, unless otherwise specified.)
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers 6 _______________________________________________________________________________________ v dd and bst operating supply current vs. frequency max5062/3/4 toc08 frequency (khz) i ddo + i bsto (ma) 900 700 800 200 300 400 500 600 100 1 2 3 4 5 6 7 8 9 10 0 0 1000 c l = 0 dh or dl output low voltage vs. temperature max5062/3/4 toc09 temperature ( c) output low voltage (v) 110 95 65 80 -10 5 20 35 50 -25 0.12 0.14 0.16 0.18 0.20 0.24 0.28 0.32 0.34 0.22 0.26 0.30 0.10 -40 125 sinking 100ma dh or dl fall time vs. temperature (c load = 10nf) max5062/3/4 toc12 temperature ( c) t f (ns) 110 95 65 80 -10 5 20 35 50 -25 10 20 30 40 50 70 110 100 90 120 60 80 0 -40 125 v dd = v bst = 8v v dd = v bst = 12v dh or dl rise propagation delay vs. temperature max5062/3/4 toc13 temperature ( c) propagation delay (ns) 110 95 65 80 -10 5 20 35 50 -25 5 10 15 20 25 35 55 60 30 45 50 40 0 -40 125 dh dl peak dh and dl source/sink current max5062/3/4 toc10 1 s/div dh or dl 5v/div sink and source current 2a/div c l = 100nf dh or dl rise time vs. temperature (c l = 10nf) max5062/3/4 toc11 temperature ( c) t r (ns) 110 95 65 80 -10 5 20 35 50 -25 12 24 36 48 60 84 108 120 72 96 0 -40 125 v dd = v bst = 8v v dd = v bst = 12v t ypical operating characteristics (continued) (typical values are at v dd = v bst = +12v and t a = +25?, unless otherwise specified.)
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers _______________________________________________________________________________________ 7 dh or dl fall propagation delay vs. temperature max5062/3/4 toc14 temperature ( c) propagation delay (ns) 110 95 65 80 -10 5 20 35 50 -25 5 10 15 20 25 35 55 60 30 45 50 40 0 -40 125 dh dl break-before-make dead time vs. r bbm max5062/3/4 toc15 r bbm (k ? ) t bbm (ns) 290 210 250 90 130 170 50 25 50 75 100 125 175 250 150 200 225 0 10 max5064 break-before-make dead time vs. temperature max5062/3/4 toc16 temperature ( c) t bbm (ns) 110 95 65 80 -10 5 20 35 50 -25 10 20 30 40 50 70 110 100 90 120 60 80 0 -40 125 r bbm = 100k ? r bbm = 10k ? max5064 delay matching (dh/dl rising) max5062/3/4 toc17 10ns/div input 5v/div 5v/div dh/dl c l = 0 delay matching (dh/dl falling) max5062/3/4 toc18 10ns/div input 5v/div 5v/div dh/dl c l = 0 dh/dl response to v dd glitch max5062/3/4 toc19 40 s/div dh dl v dd 10v/div 10v/div 10v/div 5v/div input t ypical operating characteristics (continued) (typical values are at v dd = v bst = +12v and t a = +25?, unless otherwise specified.)
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers 8 _______________________________________________________________________________________ pin name function 1 bst boost flying capacitor connection. connect a 0.1? ceramic capacitor between bst and hs for the high-side mosfet driver supply. 2d hh igh-side-gate driver output. drives high-side mosfet gate. 3h s source connection for high-side mosfet. also serves as a return terminal for the high-side driver. 4 agnd analog ground. return path for low-switching current signals. in_h/in_l inputs referenced to 5 bbm break-before-make programming resistor connection. connect a 10k ? to 100k ? resistor from bbm to agnd to program the break-before-make time (t bbm ) from 16ns to 95ns. resistance values greater than 200k ? disables the bbm function and makes t bbm = 1ns. bypass this pin with at least a 1nf capacitor to agnd. 6 in_h- high-side inverting cmos (v dd / 2) (max5064a), or ttl (max5064b) logic input. connect to agnd when not used. 7 in_h+ high-side noninverting cmos (v dd / 2) (max5064a), or ttl (max5064b) logic input. connect to v dd when not used. 8 in_l- low-side inverting cmos (v dd / 2) (max5064a), or ttl (max5064b) logic input. connect to agnd when not used. 9i n_l+ low-side noninverting cmos (v dd / 2) (max5064a), or ttl (max5064b) logic input. connect to v dd when not used. 10 pgnd power ground. return path for high-switching current signals. use pgnd as a return path for the low-side driver. 11 dl low-side-gate driver output. drives the low-side mosfet gate. 12 v dd power input. bypass to pgnd with a 0.1? ceramic in parallel with a 1? ceramic capacitor. ?p exposed pad. internally connected to agnd. externally connect to a large ground plane to aid in heat dissipation. max5064 pin description pin name function 1v dd power input. bypass to gnd with a parallel combination of 0.1? and 1? ceramic capacitor. 2 bst boost flying capacitor connection. connect a 0.1? ceramic capacitor between bst and hs for the high-side mosfet driver supply. 3d hh igh-side-gate driver output. driver output for the high-side mosfet gate. 4h s source connection for high-side mosfet. also serves as a return terminal for the high-side driver. 5 in_h high-side noninverting logic input 6 in_l low-side noninverting logic input (max5062a/c, max5063a/c). low-side inverting logic input (max5062b/d, max5063b/d). 7 gnd ground. use gnd as a return path to the dl driver output and in_h/in_l inputs. 8d l low-side-gate driver output. drives low-side mosfet gate. ?p exposed pad. internally connected to gnd. externally connect the exposed pad to a large ground plane to aid in heat dissipation (max5062c/d, max5063c/d only). max5062/max5063 pin description
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers _______________________________________________________________________________________ 9 detailed description the max5062/max5063/max5064 are 125v/2a high- speed, half-bridge mosfet drivers that operate from a supply voltage of +8v to +13.2v. the drivers are intended to drive a high-side switch without any isola- tion device like an optocoupler or drive transformer. the high-side driver is controlled by a ttl/cmos logic signal referenced to ground. the 2a source and sink drive capability is achieved by using low r ds_on p- and n-channel driver output stages. the bicmos process allows extremely fast rise/fall times and low propagation delays. the typical propagation delay from the logic-input signal to the drive output is 35ns with a matched propagation delay of 3ns typical. matching these propagation delays is as important as the absolute value of the delay itself. the high 125v input voltage range allows plenty of margin above the 100v transient specification per telecom standards. the max5064 is available in a thermally enhanced tqfn package, which can dissipate up to 1.95w (at +70?) and allow up to 1mhz switching frequency while driving 100nc combined gate-charge mosfets. figure 1. timing characteristics for noninverting and inverting logic inputs v ih v il 90% 10% v ih v il t f in_h+ dh in_h- t d_on3 t d_on4 t d_off4 t d_off3 v ih v il 90% 10% v ih v il t r t r t f in_l+ dl in_l- t d_on1 t d_on2 t d_off2 t d_off1 t match1 = (t d_on2 - t d_on1 ) or (t d_off2 - t d_off1 ) t match2 = (t d_on3 - t d_on1 ) or (t d_on4 - t d_on2 ) or (t d_off3 - t d_off1 ) or (t d_off4 - t d_off2 )
max5062/max5063/max5064 undervoltage lockout both the high- and low-side drivers feature undervolt- age lockout (uvlo). the low-side driver? uvlo low threshold is referenced to gnd and pulls both driver outputs low when v dd falls below 6.8v. the high-side driver has its own undervoltage lockout threshold (uvlo high ), referenced to hs, and pulls dh low when bst falls below 6.4v with respect to hs. during turn-on, once v dd rises above its uvlo thresh- old, dl starts switching and follows the in_l logic input. at this time, the bootstrap capacitor is not charged and the bst-to-hs voltage is below uvlo bst . for synchro- nous buck and half-bridge converter topologies, the bootstrap capacitor can charge up in one cycle and normal operation begins in a few microseconds after the bst-to-hs voltage exceeds uvlo bst . in the two-switch forward topology, the bst capacitor takes some time (a few hundred microseconds) to charge and increase its voltage above uvlo bst . the typical hysteresis for both uvlo thresholds is 0.5v. the bootstrap capacitor value should be selected care- fully to avoid unintentional oscillations during turn-on and turn-off at the dh output. choose the capacitor value about 20 times higher than the total gate capaci- tance of the mosfet. use a low-esr-type x7r dielec- tric ceramic capacitor at bst (typically a 0.1? ceramic is adequate) and a parallel combination of 1f and 0.1? ceramic capacitors from v dd to gnd (max5062_, max5063_) or to pgnd (max5064_). the high-side mosfet? continuous on-time is limited due to the charge loss from the high-side driver? quiescent current. the maximum on-time is dependent on the size of c bst , i bst (50? max), and uvlo bst . output driver the max5062/max5063/max5064 have low 2.5 ? r ds_on p-channel and n-channel devices (totem pole) in the output stage. this allows for a fast turn-on and turn-off of the high gate-charge switching mosfets. the peak source and sink current is typically 2a. propagation delays from the logic inputs to the driver outputs are matched to within 8ns. the internal p- and n-channel mosfets have a 1ns break-before-make logic to avoid any cross conduction between them. this internal break-before-make logic eliminates shoot- through currents reducing the operating supply current as well as the spikes at v dd . the dl voltage is approxi- mately equal to v dd and the dh-to-hs voltage, a diode drop below v dd , when they are in a high state and to zero when in a low state. the driver r ds_on is lower at higher v dd . lower r ds_on means higher source and sink currents and faster switching speeds. internal bootstrap diode an internal diode connects from v dd to bst and is used in conjunction with a bootstrap capacitor external- ly connected between bst and hs. the diode charges the capacitor from v dd when the dl low-side switch is on and isolates v dd when hs is pulled high as the high- side driver turns on (see the typical operating circuit ). the internal bootstrap diode has a typical forward volt- age drop of 0.9v and has a 10ns typical turn-off/turn-on time. for lower voltage drops from v dd to bst, connect an external schottky diode between v dd and bst. programmable break-before-make (max5064) half-bridge and synchronous buck topologies require that the high- or low-side switch be turned off before the other switch is turned on to avoid shoot-through currents. shoot-through occurs when both high- and low-side switches are on at the same time. this condi- tion is caused by the mismatch in the propagation delay from in_h/in_l to dh/dl, driver output imped- ance, and the mosfet gate capacitance. shoot- through currents increase power dissipation, radiate emi, and can be catastrophic, especially with high input voltages. the max5064 offers a break-before-make (bbm) fea- ture that allows the adjustment of the delay from the input to the output of each driver. the propagation delay from the rising edges of in_h and in_l to the ris- ing edges of dh and dl, respectively, can be pro- grammed from 16ns to 95ns. note that the bbm time (t bbm ) has a higher percentage error at lower value because of the fixed comparator delay in the bbm block. the propagation delay mismatch (t match_ ) needs to be included when calculating the total t bbm error. the low 8ns (maximum) delay mismatch reduces the total t bbm variation. use the following equations to calculate r bbm for the required bbm time and t bbm_error : where t bbm is in nanoseconds. rk t ns for r k ttt bbm bbm bbm bbm error bbm match . __ = ? ? ? ? ? ? < = + ? 10 8 1 200 015 ?? 125v/2a, high-speed, half-bridge mosfet drivers 10 ______________________________________________________________________________________
the voltage at bbm is regulated to 1.3v. the bbm circuit adjusts t bbm depending on the current drawn by r bbm . bypass bbm to agnd with a 1nf or smaller ceramic capacitor (c bbm ) to avoid any effect of ground bounce caused during switching. the charging time of c bbm does not affect t bbm at turn-on because the bbm voltage is stabilized before the uvlo clears the device turn-on. topologies like the two-switch forward converter, where both high- and low-side switches are turned on and off simultaneously, can have the bbm function disabled by leaving bbm unconnected. when disabled, t bbm is typi- cally 1ns. driver logic inputs (in_h, in_l, in_h+, in_h-, in_l+, in_l-) the max5062_/max5064a are cmos (v dd / 2) logic- input drivers while the max5063_/max5064b have ttl- compatible logic inputs. the logic-input signals are independent of v dd . for example, the ic can be pow- ered by a 10v supply while the logic inputs are provid- ed from a 12v cmos logic. also, the logic inputs are protected against voltage spikes up to 15v, regardless of the v dd voltage. the ttl and cmos logic inputs have 400mv and 1.6v hysteresis, respectively, to avoid double pulsing during transition. the logic inputs are high-impedance pins and should not be left floating. the low 2.5pf input capacitance reduces loading and increases switching speed. the noninverting inputs are pulled down to gnd and the inverting inputs are pulled up to v dd internally using a 1m ? resistor. the pwm output from the controller must assume a proper state while powering up the device. with the logic inputs floating, the dh and dl outputs pull low as v dd rises up above the uvlo threshold. the max5064_ has two logic inputs per driver, which provide greater flexibility in controlling the mosfet. use in_h+/in_l+ for noninverting logic and in_h-/ in_l- for inverting logic operation. connect in_h+/in_l+ to v dd and in_h-/in_l- to gnd if not used. alternatively, the unused input can be used as an on/off function. use in_+ for active-low and in_- for active-high shutdown logic. table 1. max5064_ truth table applications information supply bypassing and grounding pay extra attention to bypassing and grounding the max5062/max5063/max5064. peak supply and output currents may exceed 4a when both drivers are driving large external capacitive loads in-phase. supply drops and ground shifts create forms of negative feedback for inverters and may degrade the delay and transition times. ground shifts due to insufficient device ground- ing may also disturb other circuits sharing the same ac ground return path. any series inductance in the v dd , dh, dl, and/or gnd paths can cause oscillations due to the very high di/dt when switching the max5062/ max5063/max5064 with any capacitive load. place one or more 0.1? ceramic capacitors in parallel as close to the device as possible to bypass v dd to gnd (max5062/max5063) or pgnd (max5064). use a ground plane to minimize ground return resistance and series inductance. place the external mosfet as close as possible to the max5062/max5063/max5064 to fur- ther minimize board inductance and ac path resis- tance. for the max5064_ the low-power logic ground (agnd) is separated from the high-power driver return (pgnd). apply the logic-input signal between in_ to agnd and connect the load (mosfet gate) between dl and pgnd. power dissipation power dissipation in the max5062/max5063/max5064 is primarily due to power loss in the internal boost diode and the nmos and pmos fets. for capacitive loads, the total power dissipation for the device is: where c l is the combined capacitive load at dh and dl. v dd is the supply voltage and f sw is the switching frequency of the converter. p d includes the power dis- sipated in the internal bootstrap diode. the internal power dissipation reduces by p diode , if an external bootstrap schottky diode is used. the power dissipa- tion in the internal boost diode (when driving a capaci- tive load) will be the charge through the diode per switching period multiplied by the maximum diode for- ward voltage drop (v f = 1v). pcv fv diode dh dd sw f = () ? 1 pcv f i i v dl dd sw ddo bsto dd = ? ? ? ? ++ () 2 max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers ______________________________________________________________________________________ 11 in_h+/in_l+ in_h-/in_l- dh/dl low low low low high low high low high high high low
max5062/max5063/max5064 the total power dissipation when using the internal boost diode will be p d and, when using an external schottky diode, will be p d - p diode . the total power dissipated in the device must be kept below the maxi- mum of 1.951w for the 12-pin tqfn package, 1.5w for the 8-pin so with exposed pad, and 0.471w for the regular 8-pin so package at t a = +70? ambient. layout information the max5062/max5063/max5064 drivers source and sink large currents to create very fast rise and fall edges at the gates of the switching mosfets. the high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. use the following pc board layout guidelines when design- ing with the max5062/max5063/max5064: place one or more 0.1? decoupling ceramic capacitors from v dd to gnd (max5062/max5063) or to pgnd (max5064), and from bst to hs as close as possible to the part. the ceramic decou- pling capacitors should be at least 20 times the gate capacitance being driven. there are two ac current loops formed between the device and the gate of the mosfet being driven. the mosfet looks like a large capacitance from gate to source when the gate is being pulled low. the active current loop is from the mosfet driver output (dl or dh) to the mosfet gate, to the mosfet source, and to the return terminal of the mosfet dri- ver (either gnd or hs). when the gate of the mosfet is being pulled high, the active current loop is from the mosfet driver output, (dl or dh), to the mosfet gate, to the mosfet source, to the return terminal of the drivers decoupling capacitor, to the positive terminal of the decoupling capacitor, and to the supply connection of the mosfet driver. the decoupling capacitor will be either the flying capacitor connected between bst and hs or the decoupling capacitor for v dd . care must be taken to minimize the physical distance and the impedance of these ac current paths. solder the exposed pad of the tqfn (max5064) or so (max5062c/d and max5063c/d) package to a large copper plane to achieve the rated power dissi- pation. connect agnd and pgnd at one point near v dd ? decoupling capacitor return. 125v/2a, high-speed, half-bridge mosfet drivers 12 ______________________________________________________________________________________
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers ______________________________________________________________________________________ 13 t ypical application circuits figure 2. max5062 half-bridge conversion max5062a/ max5063a v out n n v dd = 8v to 13.2v v in = 0 to 125v v dd bst in_h in_l gnd dl dh hs pwm controller pin for pin replacement for the hip2100/hip2101 figure 3. synchronous buck converter max5064 n n v dd = 8v to 13.2v v in = 0 to 125v v out v dd bst in_h+ in_l- bbm agnd pgnd dl dh hs r bbm pwm c bbm c bst
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers 14 ______________________________________________________________________________________ t ypical application circuits (continued) figure 4. two-switch forward conversion max5064 n n v dd = 8v to 13.2v v in = 0 to 125v v out v dd bst in_h+ in_l+ bbm agnd pgnd dl dh hs pwm c bst figure 5. max5064 half-bridge converter max5064_ v out n n v dd = 8v to 13.2v v in = 0 to 125v v dd bst in_h+ in_l- bbm pgnd agnd dl dh hs r bbm pwm c bbm c bst
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers ______________________________________________________________________________________ 15 in_l in_h hs 1 2 8 7 dl gnd bst dh v dd so top view 3 4 6 5 max5062a/b max5063a/b in_l in_h hs 1 2 8 7 dl gnd bst dh v dd so-ep 3 4 6 5 max5062c/d max5063c/d 12 v dd 11 dl 10 pgnd 45 bbm 6 in_h- 1 2 dh 3 9 8 7 hs in_l+ in_l- in_h+ max5064a/ max5064b bst agnd thin qfn pin configurations max5062a max5062c gnd v dd in_h dh dl hs bst in_l 2 3 4 5 8 7 6 1 v dd /2 cmos max5064a pgnd v dd in_h+ in_l- dh dl hs bst bbm in_h- in_l+ agnd 1 2 4 3 7 8 5 6 11 10 9 12 v dd /2 cmos max5064b pgnd v dd in_h+ in_l- dh dl hs bst bbm in_h- in_l+ agnd 1 2 4 3 7 8 5 6 11 10 9 12 ttl so/so-ep max5062b/ max5062d gnd v dd in_h dh dl hs bst in_l 2 3 4 5 8 7 6 1 v dd /2 cmos so/so-ep max5063b/ max5063d gnd v dd in_h dh dl hs bst in_l 2 3 4 5 8 7 6 1 ttl so/so-ep max5063a/ max5063c gnd v dd in_h dh dl hs bst in_l 2 3 4 5 8 7 6 1 ttl so/so-ep thin qfn thin qfn functional diagrams
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers 16 ______________________________________________________________________________________ max5064a/ max5064b pwm in v out pgnd in_h+ in_l- dh dl hs bst bbm v dd in_l+ in_h- r bbm agnd c bbm v dd c bst c dd v in = 125v v dd 8v to 13.2v t ypical operating circuit part temp range pin- package top mark max5063 aasa* -40? to +125? 8 so max5063basa* -40? to +125? 8 so max5063casa* -40? to +125? 8 so-ep** max5063dasa* -40? to +125? 8 so-ep** max5064 aatc -40? to +125? 12 tqfn aaef MAX5064BATC -40? to +125? 12 tqfn aaeg ordering information (continued) part high-side driver low-side driver logic levels pin compatible max5063aasa noninverting noninverting ttl hip2101ib max5063basa noninverting inverting ttl max5063casa noninverting noninverting ttl max5063dasa noninverting inverting ttl max5064aatc both inverting and noninverting both inverting and noninverting cmos (v dd / 2) MAX5064BATC both inverting and noninverting both inverting and noninverting ttl selector guide (continued) chip information transistor count: 790 process: hv bicmos * future product? ontact factory for availability. ** ep = exposed paddle.
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers ______________________________________________________________________________________ 17 pa cka ge information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 8l, soic exp. pad.eps b 1 1 21-0111 package outline 8l soic, .150" exposed pad
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers 18 ______________________________________________________________________________________ package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 12,16,20, 24l qfn.eps e 1 2 21-0106 package outline 12,16,20,24l qfn, 4x4x0.90 mm
max5062/max5063/max5064 125v/2a, high-speed, half-bridge mosfet drivers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 19 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) e 2 2 21-0106 package outline 12,16,20,24l qfn, 4x4x0.90 mm

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